Purpose:
Discuss and share knowledge on the current landscape of low-level IPC on heterogeneous SoCs.
Discuss opportunities for improvement and alignment if that can reduce development effort / cost / risk for ECU development.
Agenda
- Presentation of one option for IPC (Cortex-R7 to Cortex-A5x cores) : Thomas Bruss (Renesas)
- Discussion of presentation
- Further discussion, driven by the questions below.
Discussion questions:
Factors affecting choice
What factors affect the choice of IPC?
- Technology / optimization?
- Tier-1 preference (previous experience)?
- Silicon Vendor preference?
- Why is a certain choice preferred?
Are there any standard ways that can be agreed upon?
Is IC-COM a standard? Are there others?
Does AUTOSAR have specific choices, and how does that apply on non-AUTOSAR systems?
Is diversity/fragmentation of IPC choice a challenge for efficient development?
What (if anything) is preventing simply agreeing on one choice?
Detailed operation
What and how does it work
e.g. shared memory, buses (SPI..), PCI, ?
Development effort: the driver must be implemented
Relationship to (other parts of) SW stack?
Flexibility (available implementation) towards upper and lower protocols (think OSI-stack).
Are higher-level protocols layered on top of the simple communication, or not? How does the choice of low-level IPC affect that?
In relation to connecting downward to hardware, what are the implementation challenges?
Required Hardware Features
Does it depend on particular hardware features (hardware-supported mailboxes, dual-port memories, com. buses,...?)
(E.g. if you choose A, then you have simple integration of technologies 1, 2, and 3, but for choice B available integrations are more limited)
Applicability
- Communication between different cores on an SoC.
- Inter-ECU? Between SoCs / CPUs.
E.g. shared PCI network,
Full network (Ethernet)